The present invention relates to a semiconductor technology and, more particularly, to a technology which is effected when applied to a semiconductor integrated circuit device having a DRAM (i.e., Dynamic Random Access Memory) and to a technology for forming the former.
A memory cell of the DRAM for latching an information of 1 [bit] is constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element. The memory cell selecting MISFET of the aforementioned memory cell is formed over the principal surface of the active regions of a semiconductor substrate (or well regions). The active regions of the semiconductor substrate are formed within the region which are surrounded by an element separating insulating film (i.e., a field insulating film) formed in the inactive regions of the aforementioned semiconductor substrate and channel stopper regions. The aforementioned memory cell selecting MISFET has its gate electrodes connected with word lines extending in a row direction. One of the semiconductor regions of the memory cell selecting MISFET are connected with complementary data lines. The other semiconductor regions are connected with one of the electrode of the aforementioned information storing capacity element. This information storing capacity element has its other electrode supplied with a predetermined potential.
The DRAM of this kind has a tendency of being integrated to have a larger capacity and having its memory cells small-sized. In case the size of the memory cells is reduced, the size of the information storing capacity element is also reduced so that the amount of charge storage or information is dropped. This reduction in the charge storage will drop the a xcex1-ray soft error withstand voltage. Therefore, it is an important technical target of the DRAM having a capacity as large as 1 [Mbit] or more to improve the a xcex1-ray soft error withstand voltage.
On the basis of this technical target, there is a tendency that-the stacked structure (i.e,. STC structure) is adopted in the information storing capacity element of the memory cell of the DRAM. The information storing capacity element of this stacked structure is constructed by laminating a lower electrode layer, a dielectric film and an upper electrode layer sequentially. The lower electrode layer is partially connected with other semiconductor region of the memory cell selecting MISFET and has its other portion extended to over the gate electrodes. The upper electrode layer is formed over the aforementioned lower electrode layer through a dielectric film. This upper electrode layer is integrated with the upper electrode layer of the information storing capacity element of the stacked structure of another adjoining memory cell so that it may be used as a common plate electrode.
Incidentally, the DRAM acting as the information storing capacity element of the stacked structure and constructing the memory cell is disclosed in U.S. application Ser. No. 07/246,514 filed on Sep. 19, 1988, for example.
We have found the following problems during the development of a DRAM having a capacity as high as 16 [Mbits].
In the DRAM, the separations of the memory cells are accomplished at present at an element separating insulating film and channel stopper regions. The element separating insulating film is formed by oxidizing the principal surface of the inactive regions of the semiconductor substrate by using a non-oxidizable mask (of a silicon nitride film) formed over the principal surface of the active regions of the semiconductor substrate. On the other hand, the channel stopper regions are formed of an impurity such as B, which is introduced into the principal surface portions of the active regions (i.e., only the memory cell array) and the inactive regions of the semiconductor substrate. This impurity is introduced, after the element separating insulating film has been formed, by the ion implantation method using such a high energy as to transmit the element separating insulating film. More specifically, the impurity introduced into the principal surface portions of the inactive regions of the semiconductor substrate below the element separating insulating film is formed as the aforementioned channel stopper regions. Since the impurity thus introduced into the principal surface portions of the active regions of the semiconductor substrate is introduced into deeper regions than the impurity introduced into the principal surface portions of the inactive regions, it will not adversely affect the memory cells. The process of forming the channel stopper regions using the ion implantation method using that high energy is featured in that it can reduce the narrow channel effect of the memory cell selecting MISFET. Specifically, the aforementioned forming process can form the channel stopper regions in self-alignment with the element separating insulating film so that it can reduce the amount of diffusion of the impurity for forming the channel stopper regions to the active regions.
However, the DRAM being developed by us is intended to have a capacity as large as 16 [Mbits] so that it cannot-retain the memory cell area and the memory cell separating area sufficiently. In other words, the aforementioned element separating insulating film has a large amount of oxidization (i.e., bird""s beak) in a transverse direction so that the area of the element separating insulating film is augmented more than necessary. This augmentation of the area of the element separating insulating film in turn shrinks the memory area more than necessary. In case, therefore, the aforementioned element separating insulating film is thinned to reduce the amount of transverse oxidization, the shallow regions of the principal surface portions of the active regions of the semiconductor substrate are doped with an impurity for forming the channel stopper regions. The impurity thus introduced into the principal surface portions of the active regions of the semiconductor substrate enhances the impurity concentration of the surface so that it fluctuates the threshold voltage of the memory cell selecting MISFET of the memory cell. As a result, the memory cell area can neither be retained, not can be shrunk the separating area of the memory cells, thus raising a problem that the DRAM cannot be highly integrated.
The present invention has the following objects:
(1) to provide a technology capable improving the degree of integration in a semiconductor integrated circuit device having a storing function;
(2) to provide a technology capable of improving the electric reliability in the aforementioned semiconductor integrated circuit device;
(3) to provide a technology capable of improving the soft error withstand voltage in the aforementioned semiconductor integrated circuit device;
(4) to provide a technology capable of reducing the number of fabrication steps in the aforementioned semiconductor integrated circuit device;
(5) to provide a technology capable of improving the treating accuracy for the fabrications in the aforementioned semiconductor integrated circuit device;
(6) to provide a technology capable of improving the drivability of the semiconductor elements in the aforementioned semiconductor integrated circuit device;
(7) to provide a technology capable of improving the fabrication yield in the aforementioned semiconductor integrated circuit device;
(8) to provide a technology capable of increasing the operating speed in the aforementioned semiconductor integrated circuit device;
(9) to provide a technology capable of preventing the defects such as the disconnections of wiring lines in the aforementioned semiconductor integrated circuit device;
(10) to provide a technology capable of improving a moisture resistance in the aforementioned semiconductor integrated circuit device;
(11) to provide a technology capable of simplifying the steps of forming redundancy fuse elements in the aforementioned semiconductor integrated circuit device;
(12) to provide a technology capable of improving the quality of films to be used in the aforementioned semiconductor integrated circuit device; and
(13) to provide an apparatus for fabricating the aforementioned item (12).
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Of the invention to be disclosed hereinafter, the reprensentatives will be briefly summarized in the following.
(1) There is provided a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of said substrate; the step of forming a second mask on and in self-alignment with the side walls of said first mask by a non-oxidizable mask thinner than the non-oxidizable mask of said first mask and an etching mask respectively; the step of etching the principal surface of said inactive regions of said substrate by using said first mask and said second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of said substrate by an oxidization using said first mask and said second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of said substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of said substrate after said first mask and said second mask have been removed.
(2) In the foregoing item (1), the step of forming said element separating insulating film is accomplished by a hot oxidization method within a range of 1,050 to 1,150xc2x0 C.
(3) There is provided a semiconductor integrated circuit device having a storing function, in which a first MISFET forming a memory cell and a second MISFET forming a peripheral circuit are formed over the principal surface of the active regions of a substrate in regions surrounded by an element separating insulating film and channel stopper regions, wherein the improvement resides: in that said inactive regions are doped with an impurity through said element separating insulating film to form a first channel stopper over the principal surface portions of the active regions of said substrate forming said first MISFET and the inactive regions surrounding said active regions; and in that the principal surface portions of the inactive regions of said substrate surrounding said active regions for forming the second MISFET are doped with an impurity to form second channel stopper regions of the same conduction type as that of said first channel stopper regions.
(4) In the foregoing item (3), said first MISFET and said second MISFET are formed over the principal surface portions of the well regions which are formed in the principal portions of said substrate and which have the same conduction type as the former but a higher impurity concentration than that of the former.
(5) There is provided a semiconductor integrated circuit device having a storing function and arranged with the individual elements of a memory cell and a peripheral circuit over the principal surface of the individual different active regions of a substrate, which are surrounded by channel stopper regions formed over the principal surface portions of inactive regions of said substrate, wherein the improvement resides: in that a first channel region enclosing said memory cell and a second channel stopper region of the same conduction type as that of said first channel stopper region are independently formed at different fabrication steps; in that the active regions such as the elements of said memory cell and said peripheral circuit or other elements are not arranged in the boundary regions of said first stopper region and said second stopper region. Said first channel stopper region and said second channel stopper region are superposed or isolated at their boundary.
(6) There is provided a semiconductor integrated circuit device including a first MISFET having the LDD structure to be used as an input/output step circuit and a second MISFET having the LDD structure and the same conduction type as that of said first MISFET to be used as an internal circuit, wherein the improvement resides: in that the used voltage of said first MISFET is made higher than that of said second MISFET, wherein the improvement resides: in that the used voltage of said first MISFET is made higher than that of said second MISFET; in that the gate length of said MISFET is made larger than that of said second MISFET; and in that the gate length of the lightly doped semiconductor regions forming the individual LDD structures of said first MISFET and said MISFET are made substantially equal.
(7) There is provided a process for fabricating a semiconductor integrated circuit device including a first MISFET having a high-voltage LDD structure to be used as an input/output step circuit and a second MISFET having a low-voltage LDD structure and the same conduction type channel as that of said first MISFET to be used as an internal circuit, comprising: the step of forming the gate insulating films and gate electrodes of said first MISFET and said second MISFET at a common step over the principal surface of the different active regions of a substrate; the step of forming lightly doped semiconductor regions having the LDD structure at a common step over the principal surface portions of the individual active regions of said substrate in self-alignment with the individual gate electrodes of said first MISFET and said second MISFET; the step of forming side wall spacers at a common step on the side walls of the individual gate electrodes of said first MISFET and said second MISFET; and the step of forming highly doped semiconductor regions on the principal surface portions of the individual active regions of said substrate in self-alignment with the individual side wall spacers of said first MISFET and said second MISFET.
(8) There is provided a semiconductor integrated circuit device including an n-channel MISFET having the LDD structure and a p-type MISFET having the LDD structure, wherein the gate length of side wall spacers, which are formed on and in self-alignment with the gate electrodes of said p-channel MISFET, is made larger than that of side wall spacers which are formed on and in self-alignment with the side walls of the gate electrodes of said n-channel MISFET.
(9) There is provided a process for fabricating a semiconductor integrated circuit device comprising a DRAM including: a memory cell constructed of a series circuit of a memory cell selecting MISFET and an information storing capacity element of the stacked structure; and a complementary MISFET having the LDD structure and constructing a peripheral circuit, comprising: the step of sequentially forming the individual gate insulating films and gate electrodes of the memory cell selecting MISFET of said memory cell and the n-channel MISFET and p-type MISFET of said peripheral circuit; the step of forming lightly doped semiconductor regions in self-alignment with said gate electrodes for forming the individual LDD structures of said memory cell selecting MISFET, said n-channel MISFET and said p-channel MISFET; the step of forming a first side wall spacer on the side walls of the individual gate electrodes of said memory cell selecting MISFET, said n-type MISFET and said p-channel MISFET; the step of forming the highly doped semiconductor regions of said n-channel MISFET in self-alignment with said first side wall spacer; the step of forming an information storing capacity element of a stacked structure of said memory cell; the step of forming a second side wall spacer on the side walls of the gate electrodes of said p-channel MISFET through said first side wall spacer and in self-alignment with said gate electrodes; and the step of forming the highly doped semiconductor regions of said p-channel MISFET in self-alignment with said second side wall spacer.
(10) In the foregoing item (9), further comprised is the step of forming an interlayer insulating film after the step of forming the highly doped semiconductor regions of said n-type MISFET and before the step of forming the information storing capacity element having the stacked structure of said memory cell, and wherein said second side wall spacer is formed of said interlayer insulating film after said interlayer insulating film has been formed.
(11) There is provided a semiconductor integrated circuit device including a DRAM having a memory cell constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element having a stacked structure, wherein the improvement resides in that the lower electrode layer of said information storing capacity element of the stacked structure at the side to be connected with one of the semiconductor regions of said memory cell selecting MISFET is constructed of the composite film which is prepared by sequentially laminating a silicon film lightly doped with an impurity for reducing the resistance and a silicon film highly doped with said impurity.
(12) There is provided a process for fabricating a semiconductor integrated circuit device having a memory cell constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element having a stacked structure, comprising: the step of doping a first-layer silicon film with an impurity for reducing a resistance after said first-layer silicon film has been deposited all over the surface of a substrate including the surface of said memory cell selecting MISFET; the second step of doping a second-layer silicon film with an impurity for reducing the resistance after said second-layer silicon film has been deposited all over said first-layer silicon film; and the step of forming the lower electrode layer of said information storing capacity element having the stacked structure by subjecting said second-layer silicon film and said first-layer silicon film individually and sequentially to a predetermined patterning by an anisotropic etching.
(13) There is provided a process for fabricating semiconductor integrated circuit device including a DRAM having a memory cell constructed of a series circuit between a memory cell selecting MISFET having one of its semiconductor regions connected with data lines and a information storing capacity element having a stacked structure and prepared by laminating a lower electrode, a dielectric film and an upper electrode layer formed over said memory cell selecting MISFET sequentially, comprising: the step of forming said upper electrode layer by depositing a silicon film-over the dielectric film of said memory cell by the CVD method and by patterning said silicon film in a predetermined manner by an anisotropic etching; and the step of forming a silicon oxide film by an oxidizing method over the surface of said upper electrode layer.
(14) There is provided a semiconductor integrated circuit device including a DRAM having a memory cell constructed of a series circuit between a memory cell selecting MISFET having one of its semiconductor regions connected with data lines and a information storing capacity element having a stacked structure and prepared by laminating a lower electrode, a dielectric film and an upper electrode layer formed over said memory cell selecting MISFET sequentially, wherein the improvement resides: in that the data lines, which are formed of a composite film by sequentially laminating a silicon film deposited by the CVD method and a transition-metal silicide film through an interlayer insulating film over the upper electrode layer of said information storing capacity element having said stacked structure, are constructed; and in that the thickness of the interlayer insulating film between said upper electrode layer and said data lines is made as large as or larger than one half of the gap interposing said upper electrode layer between the lower electrode layer of the information storing capacity element of the stacked structure of said memory cell and the lower electrode layer of said information storing capacity element of said stacked structure of another memory cell adjoining the former with the minimum gap.
(15) There is provided a semiconductor integrated circuit device having a storing function and including: complementary data lines, word lines and column select signals lines over a memory cell array; and two-layered wiring layers in the regions of a peripheral circuit of said memory cell array, wherein the improvement resides: in that the complementary data lines over said memory cell array are formed of a composite film prepared by sequentially laminating a silicon film and a transition-metal silicide film deposited by the CVD method; in that said column select signal lines are formed of a transition-metal film deposited by the sputtering method over said complementary data lines; in that said word lines are formed of an aluminum film or its alloy film deposited by the sputtering method over said column select signal lines; in that the same conducting layer as said word lines and the same conducting layer as the column select signals underlying the former are connected through a transition metal film buried by the selective CVD method in the connecting holes formed in the interlayer insulating film inbetween; in that the lower wiring lines of the two wiring lines of the regions of said peripheral circuit are formed of the same conducting layer as said column select signal lines whereas the upper wiring lines of said two wiring layers are formed of the same conducting layer as said word lines; and in that the upper and lower wiring lines of said two wiring layers are individually connected through a transition metal film buried in said connecting holes by the selective CVD method.
(16) There is provided a semiconductor integrated circuit device including: a transition-metal film buried by the selective CVD method in connecting holes formed in an underlying interlayer insulating film; and a Si-added aluminum alloy wiring lines extending over said interlayer insulating film and connected with said transition-metal film, wherein the improvement resides in that a transition-metal silicide film or a transition-metal nitride film is formed between said aluminum alloy wiring lines and said underlying interlayer insulating film including the gaps between said transition-metal film buried in said connecting hole sand said aluminum alloy wiring lines.
(17) There is provided a semiconductor integrated circuit device including: a transition-metal film buried by the selective CVD method in connecting holes formed in an underlying interlayer insulating film; and Cu-added aluminum alloy wiring lines connected with said transition-metal film and extending over said interlayer insulating film, wherein the improvement resides in that a transition-metal nitride film acting as a barrier is formed between the transition-metal film buried in said connecting holes and said aluminum-alloy wiring lines.
(18) In the foregoing items (16) and (17), a TiN film having a crystal orientation (200) is interposed between said transition-metal film buried in said connecting holes and said aluminum-alloy wiring lines.
(19) There is provided a semiconductor integrated circuit device having a passivation film formed over a wiring layer formed of an aluminum film or its alloy film, wherein the improvement resides: in that said passivation film is formed of a composite film prepared by sequentially laminating a silicon oxide film deposited by the conformal plasma CVD method using tetraethoxysilane gases as its source gases and a silicon nitride film deposited by the plasma CVD method; and in that the lower silicon oxide film of said passivation film is formed to have a thickness as large as or more than one half of the wiring gap of the regions in which the aspect ratio of said wiring gap and the thickness of said wiring lines is 1 or more.
(20) There is provided a process for fabricating a semiconductor-integrated circuit device having complementary MISFETs, comprising: the step of forming a first conductor region of a second conduction type having an impurity concentration for setting the threshold voltage of a first MISFET of a first conduction type channel and electrically separated from another region and a second semiconductor region of the first conduction type having an impurity concentration for setting the threshold voltage of a second MISFET of the second conduction type channel individually in the principal surface portions of the different regions of a semiconductor substrate; and the step of setting the threshold voltage of a third MISFET of the first conduction type channel different from the threshold voltage of said first MISFET by doping the principal surface portions of the regions of said first semiconductor regions different from said first MISFET with a threshold voltage adjusting impurity, and setting the threshold voltage of a fourth MISFET of a second conduction type channel different from the threshold voltage of said second MISFET by doping the principal surface portions of said second semiconductor regions different from said second MISFET with a threshold voltage adjusting impurity.
(21) In the foregoing item (20), said first semiconductor region and said second semiconductor region are well regions which are individually formed in self-alignment with the principal surface portions of said semiconductor substrate.
(22) There is provided a process for fabricating a semiconductor integrated circuit device, in which first and second MISFETs for generating a reference voltage and another third MISFET are individually formed to have a common conduction type channel, comprising: the step of forming a substrate or a well region with an impurity concentration for setting the threshold voltage of said first MISFET for generating said reference voltage; the step of setting the threshold voltage of said second MISFET for generating said reference voltage or the threshold voltage of said third MISFET by doping the regions of said substrate or said well regions different from said first MISFET with a threshold voltage adjusting impurity; and the step of setting the threshold voltage of said third MISFET or the threshold voltage of said second MISFET for generating said reference voltage by doping with the regions of said substrate or said well regions different from said first MISFET, said second MISFET or said third MISFET with a threshold voltage adjusting impurity.
(23) There is provided a semiconductor integrated circuit device including a DRAM arranged with memory cells formed of a series circuit between a memory cell selecting MISFET at the intersection between complementary data lines and word lines and a information storing capacity element having a stacked structure, and a laser cutting redundancy fuse element for relieving the defective ones of said complementary data lines or said word lines, wherein the improvement resides: in that said complementary data lines are formed of a composite film prepared by sequentially laminating a silicon film deposited by the CVD method and a transition-metal silicide film; and in that said laser cutting redundancy fuse elements are formed of a conducting layer shared with said complementary data lines.
(24) There is provided a process for depositing a conducting film or an insulating film over the surface of a semiconductor wafer or the surface of a silicon film deposited on the surface of said semiconductor wafer, comprising: the step of exposing the surface of said semiconductor wafer or the surface of said silicon film to the outside by cleaning the surface of said semiconductor wafer or the surface of said silicon film in a vacuum system; and the step of depositing said conducting film or said insulating film on the surface of said semiconductor wafer or the surface of said silicon film in the vacuum system shared with said cleaning step.
(25) There is provided a film depositing process for depositing an insulating film either on the surface of a semiconductor wafer or the surface of a silicon film deposited on the surface of said semiconductor wafer, comprising: the step of exposing the surface of said semiconductor wafer or the surface of said silicon film by cleaning the surface of said semiconductor wafer or the surface of said silicon film in a vacuum system by an anisotropic etching using a halogen compound; the step of irradiating the exposed surface of said semiconductor wafer or the exposed surface of said silicon film with an ultraviolet ray in the vacuum system shared with said cleaning step; and the step of depositing said insulating film on the surface of said semiconductor wafer or the surface of said silicon film in the vacuum system shared with said cleaning step.
(26) There is provided a film depositing process for depositing a silicon film on an underlying surface having a stepped shape, comprising: the step of alternately depositing a plurality of layers of a silicon film containing an impurity for reducing the resistance and a silicon film containing none of said impurity over said underlying surface; and the step of diffusing said impurity from said silicon film containing said impurity to said silicon film containing none of said impurity by subjecting the laminated silicon films to a heat treatment.
(27) There is provided a film depositing process for depositing a silicon film on an underlying surface having a stepped shape, wherein the improvement resides: in that a silicon film containing no impurity as a result of thermal decompositions is deposited by feeding silane gases at a constant flow rate in a vacuum system for depositing said silicon film; and in that said deposited silicon film is periodically doped with phosphor by feeding phosphine gases by increasing or decreasing the flow rate periodically in said vacuum system.
(28) There is provided an alignment process for aligning different three-layer patterns in an X direction and in a Y direction, wherein the improvement resides: in that the second-layer pattern is aligned in the X direction and in the Y direction with respect to the first-layer pattern underlying the former; and in that the third-layer pattern formed over said second-layer pattern is aligned in the X direction and in the Y direction with respect to the second-layer pattern underlying the former and in the Y direction and in the X direction with respect to the first-layer pattern underlying the former.
(29) There is provided a semiconductor integrated circuit device in which an interlayer insulating film is formed over an underlying surface having a stepped shape, in which first connecting holes are formed in the upper regions of the stepped shape of said underlying surface of said interlayer insulating film whereas second connecting holes are formed in the lower regions of said stepped shape, and in which wiring lines are-so extended over said interlayer insulating film that they may be connected with conducting films individually buried in said first connecting holes and said second connecting holes, wherein the improvement resides: in that the conducting films individually buried in said first connecting holes and said second connecting holes are formed of a transition-metal film which is made of a common conducting layer deposited by the selective CVD method; and in that said transition-metal film is deposited to have a thickness as large as the depth of said shallow first connecting holes.
(30) There is provided a semiconductor integrated circuit device having its wiring lines formed of a transition-metal film deposited over an underlying insulating film by the CVD method, wherein the improvement resides in that a transition-metal film of substantially the same kind as that of said wiring lines deposited by the sputtering method is formed between said underlying insulating film and said wiring lines.
(31) There is provided a semiconductor integrated circuit device having a DRAM arranged at the intersections between complementary data lines and word lines with memory cells each constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element having a stacked structure, in which a lower electrode layer, a dielectric film and an upper electrode layer are sequentially laminated, wherein the improvement resides in that an intermediate conducting film having its portion formed in self-alignment with one of the semiconductor regions of said memory cell selecting MISFET and its other portion led out over the gate electrodes of said memory cell selecting MISFET and formed below and separately of the lower electrode layer of said information storing capacity element of said stacked structure is formed between said complementary data lines and said one semiconductor region.
(32) In the foregoing item (31), said intermediate conducting film is formed to have a smaller thickness than that of the lower electrode layer of said information storing capacity element of said stacked structure.
(33) In the DRAM of the foregoing item (31), an intermediate conducting film formed of the conducting layer shared with the intermediate conducting film formed in said memory cells is interposed between the semiconductor regions of the MISFETs constructing the peripheral circuit of said DRAM and the wiring lines connected with the former.
According to the aforementioned means (1), the non-oxidizable mask of the aforementioned second mask can be thinned to reduce the amount of transverse oxidization of the element separating insulating film so that the element separating insulating film can be small-sized and thickened to increase the isolation size of the MISFETs in the depthwise direction of the substrate thereby to enhance the separatability of the MISFETs. The element separating insulating film can be thickened. Thus, when an impurity for forming the aforementioned channel stopper regions is to be introduced, the impurity to be introduced into the principal surface portions of the active regions of the substrate can be introduced deep into the substrate to reduce the fluctuations of the threshold voltage of the MISFETs as a result of the introduction of the aforementioned impurity.
According to the aforementioned second means (2), when the element separating insulating film is to be formed, the fluidicity of the silicon oxide film as a result of the hot oxidization method can be promoted to reduce the stress which is established between the element separating insulating film and the principal surface of the inactive regions of the substrate. As a result, it is possible to reduce the occurrences of the crystal defects at the corners of the grooves which are formed in the principal surface of the inactive regions of the substrate.
According to the aforementioned means (3), the threshold voltage of the parasitic MOSes can be raised at the aforementioned first channel stopper regions to retain the separating ability between the memory cells and the first MISFET and surrounding elements forming the former. At the same time, the aforementioned first channel stopper regions are formed in self-alignment with the aforementioned element separating insulating film, and the impurity for forming the first channel stopper regions can be made to have a small amount of diffusion to the active regions thereby to reduce the narrow channel effect of the aforementioned first MISFET. Since the impurity for forming the aforementioned second channel stopper regions is introduced only into the inactive regions but not the active regions for forming the aforementioned second MISFET, the influences of the substrate effect can be reduced to reduce the fluctuations of the threshold voltage. Since the second MISFET is formed to have a larger size than the first MISFET, it has a relative small amount of diffusion of the active regions for forming the second channel stopper regions to the active regions so that it raises substantially no narrow channel effect. Since, moreover, the second MISFET does not have its active regions doped with the impurity for forming the second channel stopper regions to reduce the impurity concentration in the surface of the aforementioned active regions, the threshold voltage can be reduced to augment the drivability. especially in case the second MISFET is sued as an output step circuit, the output signal level can be sufficiently retained.
According to the aforementioned means (4), the aforementioned well regions raise the impurity concentrations in the channel forming regions of the first and second MISFETs so that they can reduce the short channel effect. Since the difference between the impurity concentrations of the well regions and the aforementioned substrate, it is possible to improve the xcex1-ray soft error withstand voltage especially of the memory cells. In case, moreover, the second MISFETs construct the column address decoder circuit or the sense amplifier circuit, they can likewise improve the xcex1-ray soft error withstand voltage.
According to the aforementioned means (5), in case the aforementioned first channel stopper regions and second channel stopper regions are individually superposed at the aforementioned boundary regions, their impurity concentrations are increased. Since, however, the active regions are not arranged in the boundary regions, the junction withstand voltage between the substrate and the elements can be improved. In case, on the other hand, the first channel stopper regions and the second channel stopper regions are individually isolated at the aforementioned boundary regions, these boundary regions become liable to be formed with a large inversion layer corresponding to their area. If the active regions are present in the boundary regions, the area of the elements to be formed in the active regions is apparently increased by the addition of the aforementioned inversion layer so that the flow rate of the leakage current is augmented at the junction portions between the substrate and the elements. Since, however, the active regions are not arranged in the boundary regions, the flow rate of the leakage current can be reduced at the junction portions.
According to the aforementioned means (6), the aforementioned first MISFET has its hot carrier withstand voltage improved by enlarging its gate length so that the aging of the threshold voltage can be reduced to improve the electric characteristics. At the same time, the aforementioned second MISFET is enabled to reduce the power consumption by using a low voltage while retaining the hot carrier withstand voltage by using the low voltage. Since, moreover, the MISFET has its gate length enlarged and since the second MISFET is enabled to improve the hot carrier withstand voltage by using the low voltage, the gate length of the lightly doped semiconductor regions forming the aforementioned LDD structure can be independently controlled to substantially equalize the gate lengths of the individual lightly-doped semiconductor regions of the first MISFET and the second MISFET.
According to the aforementioned means (7), all the steps of forming the aforementioned first MISFET and second MISFET can be shared to form the individual side wall spacers at the common fabrication step so that the number of fabrication steps of the semiconductor integrated circuit device can be reduced.
According to the aforementioned means (8), the gate length of the side wall spacers of the aforementioned n-channel MISFET together with the gate length of the lightly doped semiconductor substrate forming the LDD structure so that the transmittance conductance of the n-channel MISFET can be improved to increase the operating speed. At the same time, the gate length of the side wall spacers of the p-channel MISFET can be enlarged to reduce the run-around of the highly doped semiconductor regions forming the source regions and the drain regions to the channel forming regions. As a result, the short channel effect of the p-channel MISFET can be reduced to increase the degree of integration.
According to the aforementioned means (9), the aforementioned n-channel MISFET specifies the gate length of the lightly doped semiconductor regions forming the LDD structure with the single-layered first side wall spacers so that the gate length of the lightly semiconductor regions can be reduced. The p-channel MISFET regulates the run-around of the highly doped semiconductor regions to the channel forming regions with the multi-layered first and second side wall spacers. After the heat treatment for forming the information storing capacity element of the stacked structure of the aforementioned memory cells, the highly doped semiconductor regions are formed so that the run-around of the highly doped semiconductor regions to the channel forming regions can be further reduced.
According to the aforementioned means (10), the step of forming the aforementioned second side wall spacers can be shared with the step of forming the aforementioned interlayer insulating film so that the number of steps of fabricating the semiconductor integrated circuit device can be accordingly reduced.
According to the aforementioned means (11), the lower electrode layer of the information storing capacity element of the stacked structure of the aforementioned memory cells is so thickened that the area of the side walls of the lower electrode layer can be vertically increased. As a result, the amount of charge storage can be increased to shrink the area of the memory cells thereby to improve the degree of integration. Since the impurity concentration in the surface of the upper silicon film of the aforementioned lower electrode layer is high, the amount of charge storage can be increased to improve the degree of integration likewise. Since, moreover, the impurity concentration of the silicon film of the lower electrode layer can be dropped to reduce the amount of diffusion of the impurity to one of the semiconductor regions of the memory cell selecting MISFET, the short channel effect of the memory cell selecting MISFET can be dropped to shrink the area of the memory cells thereby to improve the degree of integration better.
According to the aforementioned means (12), even the lower electrode layer of the information storing capacity element having the aforementioned stacked structure is thickened, the amount of the impurity introduced thereinto is retained to some extent and uniformed so that the anisotropy of the anisotropic etching can be enhanced while increasing the etching rate. This improvement in the anisotropy of the anisotropic etching can shrink the size of the lower electrode layer to shrink the memory cell area thereby to improve the degree of integration.
According to the aforementioned means (13), the residual of the aforementioned silicon film left unetched in the stepped portion of the underlying surface after the patterning of the silicon film can be oxidized by the subsequent oxidization step so that the aforementioned upper electrode layer and data lines can be prevented from being shorted to improve the fabrication yield. Especially if the lower electrode layer of the information storing capacity element of the stacked structure is thickened to improve the amount of charge storage, the stepped shape of the underlying surface of the upper electrode layer can be enlarged to make the aforementioned process effective.
According to the aforementioned means (14), the upper transition-metal silicide film of the aforementioned data lines is liable to experience the mutual diffusions of the impurity. As a result, the flattening of the underlying surface of the data lines cannot be promoted, but the thickness of the aforementioned interlayer insulating film can be controlled on the basis of the size of the gap between the lower electrode layers adjoining with the aforementioned minimum gap to flatten the surface of the interlayer insulating films by burying the gap between the lower electrode layers with the interlayer insulating film. As a result, the data lines can be prevented from being shorted due to the etching residual left at the stepped portion of the interlayer insulating film between the lower electrode layers, when the data lines are to be treated, to improve the electric reliability.
According to the aforementioned means (15), the complementary data lines on the aforementioned memory cell array can be excellent in the heat resistance and the non-oxidizability and can have a high step coverage of the underlying silicon film deposited by the CVD method to reduce the defects such as the disconnections. The aforementioned column select signal lines are formed over the complementary data lines so that they can be extended substantially straight without avoiding the connected portions between the complementary data lines and the memory cells. As a result, the signal transmission speed can be increased to speed up the information writing operations and the information reading operations. Since the column select signal lines are formed of a layer different from that of the complementary data lines, the wiring gap between the lower complementary data lines can be shrunk to improve the degree of integration. Since the aforementioned word lines (i.e., the shunting word lines) are made to have a lower resistance than that of the lower complementary data lines or the column select signal lines, their resistance can be reduced to increase the individual speeds of the information writing operation and the information reading operation. The transition-metal films for connecting the same conducting layer as the column select signal lines and the same conducting layer as the word lines can compensate the step coverage at the connected portions of the same conducting layer as the upper word lines to reduce the defects such as the disconnections of that conducting layer. At the same time, the stress with the underlying transition-metal film can be reduced by making the underlying conducting layer of the transition-metal film of the same kind. The lower wiring lines of the regions of the aforementioned peripheral circuit, i.e, the direct peripheral circuit (e.g., the sense amplifier circuit or the decoder circuit) of the aforementioned memory cell array can have a high migration withstand voltage, because it is made of a transition-metal film, to shrink the wiring gap thereby to improve the degree of integration.
According to the aforementioned means (16), the underlying layer of the aforementioned aluminum alloy wiring lines is uniformed over the transition-metal film buried in the aforementioned connecting hole and the interlayer insulating film so that the deposition of the Si added to the aluminum alloy wiring lines, which might otherwise come into the boundary between the transition-metal film buried in the connecting holes and the aluminum alloy wiring lines, can be reduced to reduce the resistance of the aforementioned boundary. Moreover, the transition-metal silicide film formed below the aforementioned aluminum alloy wiring lines can connect the aluminum alloy wiring lines through the cut portions, if made by the migration phenomenon at the aluminum alloy wiring lines, to reduce the defects such as the disconnections of the wiring lines.
According to the aforementioned means (17), the alloying reaction due to the mutual diffusions of the transition metal and the aluminum can be prevented at the boundary between the transition-metal film buried in the aforementioned connecting holes and the aluminum alloy wiring lines to reduce the resistance of the boundary.
According to the aforementioned means (18), the TiN film having the aforementioned crystal orientation (200) can have a smaller Si deposition than that of the TiN film having a mixed crystal orientation between (111) and (299) to reduce the resistance of the aforementioned boundary. Since, moreover, the TiN film having the crystal orientation (200) has a lower specific resistance than that of the TiN film having another crystal orientation, the resistance at the boundary can be reduced. Since the film density is high, it is possible to improve the action as the barrier.
According to the aforementioned means (19), the lower silicon oxide film of the aforementioned passivation film can be deposited at such a low temperature as to melt none of the aforementioned wiring lines and at a high step coverage so that the it can flatten the stepped shape to be formed in the aforementioned wiring layer. Thus, the silicon nitride film overlying the passivation film and having an excellent moisture resistance can be formed without any cavity based upon the aforementioned stepped shape. As a result, the no cavity is formed in the upper silicon nitride film of the passivation film to cause no cracking of the aforementioned silicon nitride film and no residual of the water content in the cavity so that the moisture resistance of the passivation film can be improved.
According to the aforementioned means (20), the threshold voltage of the aforementioned first MISFET can be set with the impurity concentration of the first semiconductor regions, and the threshold voltage of the aforementioned second MISFET can be set with the impurity concentration of the second semiconductor regions. Thus, the threshold voltage of the four kinds can be set by the twice introductions of the threshold voltage adjusting impurities so that the number of the steps of introducing the threshold voltage adjusting impurities can be reduced.
According to the aforementioned means (21), no step of exposing the surface of the semiconductor substrate other than the aforementioned well regions can be required to reduce the number of the fabrication steps accordingly.
According to the aforementioned means (22), the threshold voltage of the first MISFET for generating the aforementioned reference voltage can be set with the impurity concentration of the substrate or the well regions. Thus, the threshold voltages of the three kinds can be set by the twice introductions of the threshold voltage adjusting impurities to reduce the number of steps of introducing the threshold voltage adjusting impurities.
According to the aforementioned means (23), the aforementioned complementary data lines are formed over the aforementioned memory cell selecting MISFET and the information storing capacity element of the stacked structure so that the number of the upper insulating films of the aforementioned laser cutting redundancy fuse elements can be reduced to simplify the opening process of the upper insulating films of the laser cutting redundancy fuse elements. At the same time, the aforementioned composite film formed of the silicon film and the transition-metal silicide film has a higher laser beam absorptivity than that of the wiring lines (e.g., the aluminum wiring lines) formed over the complementary data lines so that the aforementioned laser cutting redundancy fuse elements can be easily cut.
According to the aforementioned means (24), the conducting film or the insulating film can be deposited on the surface of the aforementioned semiconductor wafer or the surface of the silicon film without being exposed to the atmosphere, after the natural silicon oxide formed on the surface of the semiconductor wafer or the surface of the silicon film has been removed by the cleaning step. Thus, the aforementioned natural silicon oxide film is not left between the surface of the semiconductor wafer or the surface of the silicon film and the aforementioned conducting film or insulating film. As a result, the conduction can be ensured between the surface of the semiconductor wafer or the surface of the silicon film and the conducting film to be deposited on the surface of the former. Moreover, the surface of the semiconductor wafer or the surface of the silicon film and the insulating film such as the dielectric film deposited on the former can be thinned to an extent to the aforementioned natural silicon oxide film (or to have a large dielectric constant in case the dielectric film is formed of a silicon nitride film) to increase the amount of charge storage of the capacity elements.
According to the aforementioned means (25), the radicals of the halogen elements sticking to the surface of the semiconductor wafer or the surface of the silicon film can be removed with the aforementioned ultraviolet ray when that surface is cleaned. Thus, it is possible to reduce the leakage current of and the change in the insulating film such as the silicon nitride film to be deposited on the surface of the semiconductor wafer or the surface of the silicon nitride film.
According to the aforementioned means (26), in the regions of the stepped shape of the aforementioned underlying surface, the step coverage of the silicon film containing the impurity can be compensated with the silicon film containing none of the impurity so that the thickness of the silicon film can be uniformed. At the same time, the aforementioned impurity can be diffused from the silicon film containing the impurity to the silicon film containing no impurity so that the multi-layered silicon film can have its large thickness retained while uniforming the impurity concentration.
According to the aforementioned means (27), the silicon film containing the impurity of the foregoing item (26) and the silicon film containing no impurity can be continuously deposited in the common vacuum system so that the throughput can be improved.
According to the aforementioned means (28), the displacement of the alignment between the aforementioned first-layer pattern and second-layer pattern and the displacement of the alignment between the first-layer pattern and the second-layer pattern can be substantially equalized to reduce the displacement of the alignment between the first-layer pattern and the third-layer pattern. As a result, in case the aforementioned alignment process is applied to the semiconductor integrated circuit device, the element size can be shrunk to an extent corresponding to the masking allowance at the fabrication step to improve the degree of integration of the semiconductor integrated circuit device.
According to the aforementioned means (29), the transition-metal film individually buried in the aforementioned first connecting holes and second connecting holes is formed to have a thickness substantially equal to the depth of the shallow first connecting holes so that none of the transition-metal film will not protrude from the first connecting holes and the second connecting holes. As a result, it is possible to improve the treating accuracy and the reliability of the aforementioned wiring lines.
According to the aforementioned means (30), the transition-metal film deposited by the aforementioned sputtering method has individually high contactnesses with the aforementioned underlying insulating film and wiring lines so that the contactness between the underlying insulating film and the wiring lines can be improved. At the same time, the transition-metal film deposited by the sputtering method is formed of a transition-metal film belonging to substantially the same kind as that of the overlying wiring lines so that the treating accuracy of the wiring lines and the underlying transition-metal film can be improved.
According to the aforementioned means (31), thanks to the interposition of the aforementioned intermediate conducting film, the memory cell area can be shrunk to improve the degree of integration to an extent corresponding to the masking allowance at the fabrication step between one of the semiconductor regions of the memory cell selecting MISFET and the complementary data lines. At the same time, the gap between the intermediate conducting film and the lower electrode layer of the information storing capacity element of the stacked structure can be eliminated to increase the area of the lower electrode layer independently of the intermediate conducting film. Thus, the memory cell area can be shrunk by increasing the amount of charge storage of the information storing capacity element of the stacked structure to improve the degree of integration.
According to the aforementioned means (32), the information storing capacity element of the stacked structure can have its lower electrode layer thickened to increase the vertical area so that the amount of charge storage can be improved to shrink the memory cell area and improve the degree of integration. At the same time, the aforementioned intermediate conducting film can be thinned to simplify the treatment.
According to the aforementioned means (33), the intermediate conducting film of the peripheral circuit can be formed at the step of forming the intermediate conducting film formed in the memory cells of the DRAM to reduce the number of fabrication steps.